Pro-Form ZE5 Specifikace

® Zylogic ZE5 Configurable System-on-Chip Platform March, 2004 (Version 1.10) Product Description © 1998-2000 by Zylogic Corporation. All rights re

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 10 DMA Transfer Count Channel 0 (CNT[15:8]) CNT15 CNT15 CNT13 CNT12 CNT11 CNT10

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 100 EExxaammppllee MMeemmoorryy IInntteerrffaaccee UUnniitt ((MMIIUU)) WWa

101 www.zylogic.com.cn MMeemmoorryy IInntteerrffaaccee UUnniitt ((MMIIUU)) TTiimmiinngg CChhaarraacctteerriissttiicc GGuuiiddeelliinneess,

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 102 AAssyynncchhrroonnoouuss MMeemmoorryy IInntteerrffaaccee TTiimmiinngg T

103 www.zylogic.com.cn CCoonnffiigguurraabbllee SSyysstteemm IInntteerrccoonnnneecctt ((CCSSII)) SSoocckkeett TTiimmiinngg GGuuiiddeelliin

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 104 CSI BusSocketDQLUT4WrSel, RdSel, SelWaitedBus ClockWaitNext Figure 62. Wa

105 www.zylogic.com.cn CCSSII SSoocckkeett TTiimmiinngg CChhaarraacctteerriissttiicc GGuuiiddeelliinneess The values listed below are repre

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 106 Guideline Guideline Speed Grade-25 -40 Description Symbol Fig. Device T

107 www.zylogic.com.cn SSiiddeebbaanndd SSiiggnnaall TTiimmiinngg CChhaarraacctteerriissttiiccss The sideband signals are controls to and fr

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 108 CCoonnffiigguurraabbllee SSyysstteemm LLooggiicc ((CCSSLL)) CCeellll (

109 www.zylogic.com.cn CCSSLL CCoommbbiinnaattoorriiaall LLooggiicc aanndd SSeeqquueennttiiaall MMooddee TTiimmiinngg CChhaarraacctteerri

11 www.zylogic.com.cn CNT23 CNT22 CNT21 CNT20 CNT19 CNT18 CNT17 CNT1676543210 Mnemonic: DMACCNT0_2 Address: FF31h Channel 1: DMA Current Count

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 110 CCoonnffiigguurraabbllee SSyysstteemm LLooggiicc ((CCSSLL)) CCeellll (

111 www.zylogic.com.cn CCoonnffiigguurraabbllee SSyysstteemm LLooggiicc ((CCSSLL)) CCeellll ((MMeemmoorryy MMooddee,, SSiinnggllee--PPoor

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 112 CKWETWS16,32TWP16,32TWH16,32TDS16,32TDH16,32TAS16,32TAH16,32TAO16,32TAO16,3

113 www.zylogic.com.cn CCoonnffiigguurraabbllee SSyysstteemm LLooggiicc ((CCSSLL)) CCeellll ((MMeemmoorryy MMooddee,, DDuuaall--PPoorrtt

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 114 CCoonnffiigguurraabbllee SSyysstteemm LLooggiicc ((CCSSLL)) CCeellll (

115 www.zylogic.com.cn BBuuss CClloocckk aanndd GGlloobbaall BBuuffffeerrss BBuuss CClloocckk aanndd GGlloobbaall BBuuffffeerrss FFuun

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 116 PPrrooggrraammmmaabbllee IInnppuutt//OOuuttppuutt ((PPIIOO)) TTiimmiinng

117 www.zylogic.com.cn OOuuttppuutt PPaatthh CChhaarraacctteerriissttiiccss The values listed below are representative, guideline values extr

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 118 Output Buffer Switching Characteristics 01020304050600.0 0.5 1.0 1.5 2.0 2.

119 www.zylogic.com.cn Ordering Information TE5 20 S 40 - 40 Q CTriscend E5ConfigurableSystem-on-ChipFamilyConfigurableSystem Logic(CSL) Cells x

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 12 Channel 0: DMA Pending Requests Channel 0 (REQ[7:0]) REQ7 REQ6 REQ5 REQ4 REQ

® ZZyyllooggiicc ZZEE55 CCoonnffiigguurraabbllee SSyysstteemm--oonn--CChhiipp FFaammiillyy C O N T E N T S OVERVIEW ...

Zylogic ZE5 Configurable System-on-Chip Platform ii Six Global Buffers...54 Clock and Global Signal Stoppin

iii ZYLOGIC ZE5 SWITCHING CHARACTERISTIC GUIDELINES ...95 General ZE5 Timing Characteristi

13 www.zylogic.com.cn This register is shared by both DMA channels. Cleared by a power-on reset or other device-wide reset. IInntteerrffaacciinn

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 14 REQSELENBLSELConfigurableSystem LogicDMA Select RegisterDMA0 REQRequest toDM

15 www.zylogic.com.cn Configurable System Interconnect (CSI) Bus The Configurable System Interconnect (CSI) bus, shown in Figure 9, bridges th

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 16 AAddddrreessss BBuuss All 32 address bits are presented via the CSI inter-

17 www.zylogic.com.cn AAddddrreessss SSppeecciiffiiccaattiioonn The MATCH0 and MATCH1 register values are automatically defined by the Zylogic

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 18 DDMMAA CCoonnttrrooll A selector provides a relocatable control register f

19 www.zylogic.com.cn trix may require wait-states, either because the “soft” module handshakes with another asynchro-nous device or if the “sof

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 2 - Embedded debugging capabilities  Embedded Configurable System Logic (CSL

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 20 onto the Data Read output bus, part of the CSI socket. Bus ClockRdSelDATADat

21 www.zylogic.com.cn Timer 1 external input T1 External I/O for Timer 2 T2 Timer/Counter 2 capture/reload trigger or an additional external i

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 22 Configurable System Logic (CSL) The Configurable System Logic (CSL) matrix

23 www.zylogic.com.cn Table 6. CSL Banks by Device. CSL Banks Part Number Columns Rows Total Total CellsZE502 2 1 2 256 ZE505 2 2 4 512 ZE512

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 24 RoutingMatrixRoutingMatrixRoutingMatrixRoutingMatrixCSL CellCSL Cell8 Short

25 www.zylogic.com.cn GGeenneerraall--ppuurrppoossee IInntteerrccoonnnneecctt The general-purpose interconnect, shown in Figure 22, distribute

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 26 CCSSLL CCeellll CCaappaabbiilliittiieess A CSL cell, as shown in Figure 2

27 www.zylogic.com.cn (X≥Y)

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 28 Table 9. Logic functions implemented in a CSL cell. Class Function CSL Cell

29 www.zylogic.com.cn MMeemmoorryy FFuunnccttiioonnss In memory mode, a CSL cell performs various memory functions, including single- and dual

3 www.Zylogic.com  Four-pin IEEE 1149.1 JTAG interface port for download and debugging - Supports SAMPLE/PRELOAD, EXTEST, IN-TEST, BYPASS, an

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 30 SSiinnggllee--PPoorrtt RRAAMM ((RRAAMM1166XX11,, RRAAMM3322XX11)) As a s

31 www.zylogic.com.cn Programmable Input/Output (PIO) Pins Programmable input/output blocks (PIOs) interface external package pins to internal f

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 32 First, the ZE5 has a dedicated external memory interface, separate from the

33 www.zylogic.com.cn PPIIOO OOuuttppuutt SSiiddee Output signals can be optionally inverted within the PIO, and can pass directly to the pad

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 34 JJTTAAGG SSuuppppoorrtt Embedded logic attached to the PIOs contains test

35 www.zylogic.com.cn The main features of the memory interface unit are:  Support for a standard 256Kx8 external mem-ory interface  Suppor

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 36 BUSCLKCE-OE-WE-D[7:0]VALID VALIDSETUP STROBE Figure 33. One-cycle write ope

37 www.zylogic.com.cn SER_WR is used to program a FLASH- or EEPROM-based external serial sequential-access PROM. Cleared by a power-on reset or

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 38 RPW[2:0] specifies the pulse width of OE- during a memory read sequence. Th

39 www.zylogic.com.cn Mappers respond to accesses within a selectable zone of logical addresses. The zones refer to a range of addresses. The

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 4 The embedded SRAM-based Configurable System Logic (CSL) matrix provides "

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 40 A[7:0]A[15:8]8032 Logical AddressZONEBLOCK SIZEENABLE=A[31:0]CSI Bus Physica

41 www.zylogic.com.cn The block size results in a mask used during ad-dress matching. The block size is specified as the log base two of the de

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 42 CC11,, CC22 –– FFuullllyy pprrooggrraammmmaabbllee ccooddee mmaappppee

43 www.zylogic.com.cn The D0 mapper has one programmable CRU reg-ister, DMAP0_TAR. The content of DMAP0_TAR is placed on the A[31:24] physical

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 44 DD55 TTaarrggeett AAddddrreessss ((MMiidd BByyttee)) A23 A22 A21 A20 A1

45 www.zylogic.com.cn Mnemonic: XMAP_TAR_1 Address: FE21h SSFFRR EExxppoorrtt TTaarrggeett AAddddrreessss ((LLaattcchh IInnssttrruuccttiio

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 46 mechanism (J_INTR). For additional details, refer to the “Reset Conditions”

47 www.zylogic.com.cn The JTAG port can also be used to initialize the CSoC or to update external memory devices con-nected to the MIU port. Us

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 48 Configuration Register Unit (CRU) The Configuration Register Unit (CRU) cont

49 www.zylogic.com.cn Slave Passive Downloaded by other controller through bus inter-face. PPaarraalllleell MMooddee Parallel mode initializat

5 www.zylogic.com.cn executed from internal RAM, offering faster access plus security in battery-backed applications. The majority of the system

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 50 The serial memory interface requires only four in-terface signals. D0/SDIN -

51 www.zylogic.com.cn With the help of the microcontroller, the JTAG port can also program an external Flash memory. In the Flash programming m

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 52 There is unrestricted write access to this register, a read is not required.

53 www.zylogic.com.cn Table 28. Estimated Parallel Initialization Times at Various Bus Clock Frequencies. Bus Clock Frequency Device 1 MHz 5

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 54 C1C2XTALXTALINBCLK/XTALBCLKXTALPWDSEL.4R1 Figure 44. Crystal oscillator inp

55 www.zylogic.com.cn ter, is also used in Multiply and Divide instructions. The ALU generates several status signals that are stored in the Pr

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 56 WWoorrkkiinngg RReeggiisstteerrss There are four sets of working registers

57 www.zylogic.com.cn SSppeecciiaall FFuunnccttiioonn RReeggiisstteerrss The 8032 uses Special Function Registers (SFRs) to control and monit

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 58 instructions using DPTR will then access DPL1 and DPH1 in place of DPL and D

59 www.zylogic.com.cn the interrupt was edge triggered. Otherwise, it tracks the value that appears the INIT0 sideband signal. IT0 is the Inter

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 6 TTiimmeerrss The ZE5's 8032-based microcontroller has three 16-bit time

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 60 T1M is the Timer 1 clock select bit. When T1M is set to 1, Timer 1 uses a d

61 www.zylogic.com.cn SADDR is used only during multiple MCU opera-tions involving the serial port. SADDR is loaded with the given or broadcast

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 62 Timer 2 by clearing this bit preserves the current count value in TH2, TL2.

63 www.zylogic.com.cn F0 is User flag 0, a general-purpose flag that can be set or cleared by the user by software. RS.1-0 select the active Reg

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 64 EExxtteennddeedd IInntteerrrruupptt EEnnaabbllee - --EWDI----76543210 Mne

65 www.zylogic.com.cn The bits in these SFRs are addressed by adding the bit position to the SFR address. Example: MOV 20h, 21h ; Move co

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 66 AAbbssoolluuttee AAddddrreessssiinngg Absolute addressing is used to speci

67 www.zylogic.com.cn rupt. However there is a predefined hierarchy among the interrupts themselves. This hierarchy helps the interrupt contro

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 68 LCALL. The vector addresses for the different sources are as shown in Table

69 www.zylogic.com.cn From the time an interrupt source is activated, the longest response time is 12 machine cycles. This includes  1 machi

7 www.zylogic.com.cn itself with a particular channel through a DMA con-trol register (DMACTRL), which contains a request and acknowledge signal

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 70 JTAG-initiated condition is cleared once the com-mand is no longer asserted.

71 www.zylogic.com.cn SFR Name Reset Value TCON 00000000b TH0 00000000b TH1 00000000b TH2 00000000b TL0 00000000b TL1 00000000b TL2 00000000b T

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 72 After a reset condition, the program counter is re-set to 0000h and all the

73 www.zylogic.com.cn crystal and set the MIU read timing parameters to the pre-power-down values. Table 42 summarizes the sequence for entering

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 74 an interrupt service routine (ISR) for the corre-sponding external interrupt

75 www.zylogic.com.cn  Added information about pin directionality during initialization to Pin Description.  Added additional information on

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 76 Pin Description Table 43 describes the pins available on an ZE5 configurable

77 www.zylogic.com.cn Pin Name Pin Description Parallel Serial Slave GNDIO Ground connection for I/O functions; connect to ground for intern

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 78 Pin Name Pin Description Parallel Serial Slave TMS JTAG Test Mode Select

79 www.zylogic.com.cn Pin Name Pin Description Parallel Serial Slave VCC Supply voltage for internal logic functions, separate from I/O. Co

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 8 can be combined to form more complex and pow-erful operations. SSiinnggllee

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 80 112288--ppiinn TThhiinn PPllaassttiicc QQuuaadd FFllaatt PPaacckk,, tt

81 www.zylogic.com.cn 112288--ppiinn tthhiinn PPQQFFPP ((PPaacckkaaggee CCooddee==LL)) PPaacckkaaggee PPiinnoouutt TTaabblleess Shaded c

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 82 112288--PPiinn LLQQFFPP PPiinnss bbyy TTyyppee PPaarraalllleell MMoodd

83 www.zylogic.com.cn 112288--ppiinn tthhiinn PPQQFFPP ((PPaacckkaaggee CCooddee==LL)) PPaacckkaaggee MMeecchhaanniiccaall DDrraawwiinngg

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 84 220088--ppiinn PPllaassttiicc QQuuaadd FFllaatt PPaacckk,, ttoopp vvii

85 www.zylogic.com.cn 220088--ppiinn PPQQFFPP ((PPaacckkaaggee CCooddee==QQ)) PPaacckkaaggee PPiinnoouutt TTaabblleess Shaded cells repre

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 86 Pin ZE505 ZE512 ZE520 ZE532 151 SLAVE- SLAVE- 152 OE-/SRST OE-/SRST 153 CE-

87 www.zylogic.com.cn 220088--ppiinn PPQQFFPP ((PPaacckkaaggee CCooddee==QQ)) PPaacckkaaggee MMeecchhaanniiccaall DDrraawwiinngg 15253 10

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 88 112288--ppiinn LLQQFFPP aanndd 220088--ppiinn PPQQFFPP LLaanndd PPaatt

89 www.zylogic.com.cn 448844--bbaallll BBaallll--GGrriidd AArrrraayy PPaacckkaaggee,, ttoopp vviieeww tthhrroouugghh ttoopp ooff ppaacc

9 www.zylogic.com.cn CRC signature can be compared with the expected value. The CRC logic uses a CRC-CCITT 16-bit divisor polynomial, as shown i

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 90 448844--bbaallll BBaallll--GGrriidd AArrrraayy ((PPaacckkaaggee CCooddee

91 www.zylogic.com.cn Ball Pin Name M17 GNDIO M22 GNDIO M23 GNDIO M24 N.C. M25 N.C. M26 PIO N1 PIO N2 N.C. N3 N.C. N4 VCC N5 VCC N10 GND

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 92 Ball Pin Name AE19 PIO/GBUF1 AE20 PIO AE21 N.C. AE22 PIO AE23 PIO AE24 PIO

93 www.zylogic.com.cn 448844--ppiinn BBGGAA ((PPaacckkaaggee CCooddee==BB)) PPaacckkaaggee MMeecchhaanniiccaall DDrraawwiinngg 126BASee D

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 94 Electrical and Timing Characteristics AAbbssoolluuttee MMaaxxiimmuumm RRaa

95 www.zylogic.com.cn Note 7: Capacitance and inductance is sample-tested only. Zylogic ZE5 Switching Characteristic Guidelines All Zylogic devi

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 96 JJTTAAGG IInntteerrffaaccee TTiimmiinngg CChhaarraacctteerriissttiiccss

97 www.zylogic.com.cn Speed Grade All -25 -40 Description Symbol Device Min [1] Max MaxUnits ZE502 2.0 24.0 17.5 ns ZE505 2.0 24.0 17.5 ns Z

Zylogic ZE5 Configurable System-on-Chip Platform www.Zylogic.com.cn 98 ZE505 4.5 6.0 ns ZE512 4.5 6.0 ns flop or latch using the Bus Clock Input as

99 www.zylogic.com.cn GGlloobbaall BBuuffffeerr,, IInnppuutt SSeett--UUpp aanndd HHoolldd INFFGBUFxPIOGlobalBuffer Figure 53. PIO setup t